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Journal of Electrical and Computer Engineering Volume 2018 ,2018-11-15
A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor
Research Article
Chen Cai 1 , 2 Jian-zhong Zhao 2 Yu-mei Zhou 1 , 2
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DOI:10.1155/2018/3095950
Received 2018-07-15, accepted for publication 2018-11-01, Published 2018-11-01
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摘要

The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive equalization system with optimized eye-opening monitor is proposed. The designed eye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm, and the eye diagram is obtained by undersampling with the low-speed asynchronous clock. With the eye-opening monitor into the adaptive loop, an adaptive equalization system combined with continuous-time linear equalization (CTLE) is completed. And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. And postsimulation results show that it can offer compensation from 6 to 21 dB for 1.25–12.5 Gbps range of receiving data, which achieves a large range of data rate and channel loss, and its power efficiency is 0.046 pJ/bit/dB for the worst case, which is better than most previous works.

授权许可

Copyright © 2018 Chen Cai et al. 2018
This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

图表

Channel frequency characteristic.

Eye diagrams and statistic bars. (a) Optimal equalization. (b) Over equalization.

Eye diagrams and statistic bars. (a) Optimal equalization. (b) Over equalization.

Asynchronous undersampling technique.

Proposed adaptive equalizer structure.

Proposed adaptive equalizer structure’s adaptation control flow chart.

CTLE circuit. (a) Conventional CTLE circuit and frequency-response curve. (b) CTLE with inductor peaking. (c) Designed CTLE circuit and frequency-response curve.

CTLE circuit. (a) Conventional CTLE circuit and frequency-response curve. (b) CTLE with inductor peaking. (c) Designed CTLE circuit and frequency-response curve.

CTLE circuit. (a) Conventional CTLE circuit and frequency-response curve. (b) CTLE with inductor peaking. (c) Designed CTLE circuit and frequency-response curve.

Circuit of full differential comparator and DAC.

Circuit of full differential comparator and DAC.

Layout of the chip.

Postsimulation results of adaptive equalization for different data rates and channel losses.

Postsimulation results of adaptive equalization for different data rates and channel losses.

Postsimulation results of adaptive equalization for different data rates and channel losses.

Postsimulation results of adaptive equalization for different data rates and channel losses.

Postsimulation results of adaptive equalization for different data rates and channel losses.

Postsimulation results of adaptive equalization for different data rates and channel losses.

通讯作者

Yu-mei Zhou.Institute of Microelectronics of Chinese Academy of Sciences, Beitucheng West Road, Chaoyang District, Beijing 100029, China, cas.cn;University of Chinese Academy of Sciences, Yuquan Road, Shijingshan District, Beijing 100049, China, ucas.ac.cn.ymzhou@ime.ac.cn

推荐引用方式

Chen Cai,Jian-zhong Zhao,Yu-mei Zhou. A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor. Journal of Electrical and Computer Engineering ,Vol.2018(2018)

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